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After approximately half a century of development, HgCdTe infrared detectors have become the first choice for high performance infrared detectors, which are widely used in various industry sectors, including military tracking, military reconnaissance, infrared guidance, infrared warning, weather forecasting, and resource detection. Further development in infrared applications requires future HgCdTe infrared detectors to exhibit features such as larger focal plane array format and thus higher imaging resolution. An effective approach to develop HgCdTe infrared detectors with a larger array format size is to develop the small pixel technology. In this article, we present a review on the developmental history and current status of small pixel technology for HgCdTe infrared detectors, as well as the main challenges and potential solutions in developing this technology. It is predicted that the pixel size of long-wave HgCdTe infrared detectors can be reduced to 5 μm, while that of mid-wave HgCdTe infrared detectors can be reduced to 3 μm. Although significant progress has been made in this area, the development of small pixel technology for HgCdTe infrared detectors still faces significant challenges such as flip-chip bonding, interconnection, and charge processing capacity of readout circuits. Various approaches have been proposed to address these challenges, including three-dimensional stacking integration and readout circuits based on microelectromechanical systems.
Over the past several decades, various types of HgCdTe infrared (IR) detector imaging systems have been developed to meet the demand of industry applications, which is shown in Fig.
Although improving the optical aperture of the system is the basic method to achieve higher spatial resolution or larger detection distance, this will lead to a significant increase in system size, weight, and cost, which are not desirable for practical industry applications. Therefore, it is essential to fabricate HgCdTe FPAs with larger format size to achieve high imaging resolution. Currently, there are two main approaches to develop HgCdTe FPAs with large array format size. One is to grow the HgCdTe material on substrates with large wafer size. A significant amount of work has been conducted in this area, and HgCdTe IR materials were grown on various alternative substrates, including Si, Ge, and GaAs. However, owing to the large lattice mismatch between these alternative substrates and the HgCdTe material, there are high densities of dislocations generated in the HgCdTe layers that were grown, which degrades the device performance of HgCdTe IR detectors, especially long-wave IR (LWIR) detectors.[4,5] Although GaSb was proposed as a new alternative substrate for developing high quality HgCdTe materials with lower dislocation density, and significant progress has been made with these GaSb alternative substrates,[6–10] there are still considerable developments required before successfully applying them to industry applications. The second approach is to reduce the pixel size of the HgCdTe detector. Even with the existing HgCdTe wafer size, the array size will increase by a factor of four when the pixel size is reduced by half, which will significantly increase the array format size and thus the imaging resolution. A reduction in pixel size can also reduce the production cost of the FPAs by fabricating more FPA chips out of a single wafer. For an existing array size, a reduction of the pixel size by half will reduce the detector chip area by a factor of four, significantly reducing the chip size as well as the cooling requirements of the dewar package. This effect will be more obvious by increasing the array size.
In addition, when the system imaging resolution is limited by the detector, the modulation transfer function (MTF) of the detector can also be improved by reducing the pixel size or center distance of the detector in the FPAs, further, the detection system can be improved to the near diffraction limit performance without increasing the optical aperture, resulting in a spatial resolution or target detection distance close to the near diffraction limit. When the optical system reaches the diffraction limit, the diffraction image presents a bright central circular spot, called as an Airy circle, which contains 84% of the radiation flux, with the rest in the surrounding ring. The diameter of the Airy circle D is defined as D = 2.44 λF, where λ is the wavelength, and F is the F number of the optical system. Under the premise of ensuring the optical aperture and MTF of the optical system, the smaller the pixel size, the higher the resolution. It should be noted that because of the limitation of the Airy diameter and the fabrication process of the detector, there is a fundamental limit for the pixel size reduction. The conventional imaging methods require the detector pixel size to be equal to the diameter of the Airy circle. To study the influence of the pixel size on the system imaging quality, DRS Corporation in the US has undertaken an extensive theoretical analysis and experimental verification and confirmed the possibility of reducing the detector pixel size to near-diffraction limit or even ultra-diffraction limit. The minimum pixel sizes of the detector were estimated by assuming F/d = 2 as the optimum resolution condition, which is listed in Table
As discussed above, small pixel detector technology presents an important technology for the future development of HgCdTe IR detectors. Significant progress has been made in this area over the past decades by the main industry manufacturers in the world. In the following section, we will review the research progress at certain primary research institutions and detector manufacturers.
Sofradir has become one of the major manufacturers for HgCdTe IR detectors in the world by demonstrating its capability to produce imaging systems with high performance and reliability.[12] In 1986, Sofradir started manufacturing the second-generation HgCdTe linear detector arrays. In 1991, Sofradir demonstrated one of their best sellers: 288 × 4 HgCdTe CCD detectors with pixel sizes of 25 μm (scan direction) and 28 μm (cross-scan direction). Subsequently, they developed the 480 × 6 complementary metal–oxide semiconductor (CMOS) HgCdTe IR FPAs with pixel sizes of 28 μm (scan direction) and 38 μm (cross-scan direction),[13] which later became a part of the horizontal technology integration program in the US. In 1999, CEA-LETI/LIR developed the MWIR and LWIR 1500 × 1 HgCdTe FPAs. The pixels had a square active surface of 30 μm × 30 μm and were laid out in a staggered configuration with a cross-scan pitch of 30 μm and an in-scan pitch of 60 μm, which is shown in Figs.
In 1991, Sofradir started developing HgCdTe starring arrays with the first demonstration of a 64 × 64 array with a pitch of 60 μm in both directions.[14] In 1992, 128 × 128 starring arrays were demonstrated for both MWIR and LWIR wave bands. Typically, the pixel in the 128 × 128 starring array was square in shape with a pixel size of 50 μm. The 128 × 128 HgCdTe IR FPAs were operated in both the snapshot mode and integrate-then-read mode. For the LWIR detector arrays, two central sub-formats (64 × 64 and 32 × 32 windowing) enabled an increased frame rate. In the meantime, owing to the increased demand for missile applications, larger arrays such as the 320 × 256 format were developed with the representative product of 320 × 256 MWIR detector arrays, which had a pixel size of 30 μm and were cooled with a Stirling microcooler.[15] The US television format of 640 × 480 FPAs was later developed at CEA/LETI LIR in 1997 and then manufactured at Sofradir in 1999 with a pitch size of 25 μm, which is shown in Fig.
The first HgCdTe FPA with a pixel size of 15 μm was introduced to the market in 2004, which had a 640 × 512 format and was operated in the MWIR (3–5 μm) band. This product titled Scorpio was created by using liquid phase epitaxy (LPE) method with an enhanced process to reduce the dispersion of response. The production was soon transferred to molecular beam epitaxy (MBE) process by the end of 2008. For applications in systems requiring higher spatial resolution like surveillance, Sofradir developed its Jupiter model which had a 1280 × 1024 format with a pixel size of 15 μm operated in the MWIR band and cooled by a linear flexure bearing split Stirling cooler from Thales Cryogenics, which is shown in Fig.
In 2014, Sofradir launched its Daphnis-HD HgCdTe FPAs (as shown in Fig.
After nearly 30 years of development, Sofradir has produced IR detector components with the FPA pixel size reduced from 60 μm to 10 μm and pixel number increased from thousands to millions. During this period, numerous new technologies have emerged to promote the development of IR focal plane, including the world’s first demonstration of small pixel technology. However, with the further reduction of pixel size, device processing technology and readout circuit design are facing great technical challenges, which will be the key factors limiting the development of small pixel technology.
Raytheon is another major HgCdTe IR detector manufacturer in the world. As indicated in the literature, Raytheon launched its second and third generation IR detectors in the 1980s with pixel sizes ranging from 61 μm to 38 μm (as shown in Fig.
At Raytheon, the 20 μm pixel technology was also used in two-color HgCdTe FPAs since the 2000s. As shown in Fig.
Raytheon’s technological roadmap of IR focal plane has always represented the most “complex” and “state-of-the-art” technologies. However, the development of smaller pixels seems to have slowed down from its original R&D pace. A variety of planar array formats were designed and produced at the pitch size of 20 μm, and the largest FPA has reached 4 K × 4 K format with more than ten million pixels. However, it should be noted that, under the same pixel size, a larger format requires exponential growth of FPA size, and this presents a series of challenges during material profile, flip-chip-bonding, interconnection, and so on. Further reduction of the pixel size can reduce the total size of the FPA and make the FPA easier to manufacture.
At DRS Corporation, the technology of high-density vertical integration photodetector (HDVIP) was developed for fabricating high-performance HgCdTe IR FPAs with a pixel size ranging from 20 μm to 15 μm, 12 μm, and even smaller size. The HDVIP structure included a channel through the HgCdTe film, ending at the readout integrated circuit (ROIC). The p-type HgCdTe was transformed to form a columnar n-type region around the channel, and an n+/n/p diode was obtained (as shown in Fig.
The unique technology of DRS changed the placement of a p–n junction and achieved a new type of device architecture. On this basis the pixel size was minimized to 6 μm, which is the smallest size in known IR FPAs. This type of lateral device geometry could reduce the effective area of the absorption region and might also decrease the absorption efficiency.
SELEX based in UK is another major HgCdTe FPA manufacturer. To reduce the power consumption and production cost as well as enhance the imaging resolution, over the years SELEX has developed HgCdTe IR FPAs operating in various wavelength ranges (short-wave IR, LWIR, MWIR, and dual waveband IR) and with various pixel sizes ranging from the initial 30 μm to 24/20/16 μm,[27] as shown in Fig.
While being different from MBE and LPE methods, the metalorganic chemical vapor deposition (MOCVD) growth demonstrates faster material preparation speed and provides a new way of producing HgCdTe. The FPAs manufactured from MOCVD-grown materials have already reached a pixel size of 8 μm and pixel number of millions. However, only a small portion of FPAs have been prepared by this process and its transferability and reproducibility need to be verified.
In comparison to visible light sensors whose pixel size was already reduced to 1.4 μm, there is a significant challenge in scaling down the pixel size of HgCdTe IR detectors. By reducing the dimension of the HgCdTe pixels, the fabrication and integration processes become considerably challenging, including flip-chip bonding, and signal processing (ROIC, signal integral capacitance, and signal to noise ratio (SNR)). The flip-chip bonding for small pixel detectors is significantly challenging, especially when the pixel size is below 8 μm, which can seriously degrade the pixel and array yield and thus increase the production cost. Therefore, it is essential to develop reliable flip-chip bonding processes that are suitable for small pixel detectors. A potential solution is a three-dimensional (3D) integration technology using controlled flip-chip bonding and wafer bonding. Recently, multiple layers of CMOS (up to three layers) were stacked and vertically interconnected, potentially increasing the processing volume within the pixel area. In addition, 3D integration process using wafer bonding was demonstrated for integrating small pixel detectors (approximately 6 μm) on Si and InP.[30]
In traditional analog ROIC technology, the photocurrent generated by the IR detectors is accumulated and stored locally on the capacitors (electron potential well). The maximum charge stored during the integration time is equal to the product of the total capacitance and the maximum permissible voltage across the capacitor. Figure
With small pixels, the photon flux was reduced and as a result the integration time was usually increased to achieve high quality imaging. Because of this, the imaging quality of remote devices with smaller instantaneous fields of view was often limited by the moving halos, which is the consequence of the movement of the hand during the integration time. In this case, short integration time (2–5 ms) should be used to reduce the influence on the detection distance. Short integration time was also useful for freezing targets that move fast. Conversely, the integration time could be longer for a stabilization system (10 ms) being independent of platform deployment and vibration. To achieve high sensitivity (i.e., < 30 mK), the 5 μm pixel LWIR HgCdTe FPA required a large amount of integrated charge to be accommodated in a very small unit. With the traditional ROIC design, the charge storage density was approximately 2.5 × 104 e/μ m2, which provided high sensitivity (< 30 mK) for most tactical MWIR and LWIR applications, e.g., a pixel size of 12 μm.[32] For a 5 μm pixel size, the charge stored with the standard ROIC technology was less than million electrons, however, for high sensitivity applications, 8–12 million electrons were required. Therefore, the small pitch HgCdTe infrared detectors are currently not widely available for practical applications.
The microelectromechanical system (MEMS) capacitors are suitable for 3D ROIC design and provide a potential solution to the problem of charge storage in small pixel detectors. In recent years, the 0.18 μm Si CMOS technology was used in developing the charge capacity control technology for the metal–insulator–metal (MIM) capacitors with a charge density of 2 fF/μm2. Multilayer stacking of MIM capacitors can have a higher charge density of up to approximately 7 fF/μm2. The 15 μm pitch of 640 × 512 ROIC designed by AIM Corporation using the 0.18 μm Si-CMOS technology has significantly enhanced the NETD performance of HgCdTe IR detectors in comparison to the standard ROIC, the results of which are shown in Fig.
To maintain or improve the dynamic range of a unit pixel, it is essential to have CMOS technology with progressive scale and higher density. High density CMOS fabrication processes could be used to improve the unit processing capacity. Figure
Furthermore, with the reduction of HgCdTe pixel size, new challenges are expected to arise, such as the following issues. (i) When the pixel size is reduced to be comparable to the size of material defects (approximately 5 μm), the influence of the dark current caused by the material defect becomes more significant and damaging. Therefore, the production of HgCdTe materials with ultralow defect density has become one of the major challenges in developing small pixel technology. (ii) Traditional contact lithography has a considerably high requirement of the chip surface roughness. Owing to the square shape of the HgCdTe materials, edge bead is severe during spin coating of the photoresist on HgCdTe, resulting in an uneven material and a photo mask that is not completely in contact with the material surface. Therefore, this leads to distortion of transferred patterns. When the pixel size decreases, the critical size during fabrication decreases as well, and the distortion and inconsistency of the photolithography are amplified, which leads to the deviation of the sizes of injection area and contact hole from the design value, thus greatly affecting the pixel uniformity in an FPA. (iii) HgCdTe FPAs normally utilize common ground, which makes the insulation between two adjacent pixels poor. When subjected to IR radiation, photo-generated carriers will diffuse to adjacent pixels, causing electrical crosstalk. When the pixel size is reduced, the electrical crosstalk between neighboring pixels becomes significantly worse. Therefore, the device structure and layout of the FPA need to be redesigned and simultaneously the processing steps need to be adjusted to modify the material electrical properties to reduce the crosstalk.
In summary, we have presented a detailed review on the small pixel technology for HgCdTe IR detectors. The small pixel technology represents an important development trend for HgCdTe IR detectors owing to its capability in fabricating HgCdTe FPAs with larger array format and thus higher imaging resolution, which can have various important applications, such as remote target recognition under low F number conditions. It was predicted that the pixel size of LWIR HgCdTe detectors can be reduced to 5 μm, while that of MWIR HgCdTe detectors can be reduced to 3 μm. However, it is very challenging to develop small pixel HgCdTe IR detectors owing to the difficulty and limitations in flip-chip bonding, interconnection, and charge processing capacity of readout circuits. Various approaches were proposed to address these challenges, including 3D stacking integration, ROIC MEMS technology, low defect density HgCdTe thin film material growth technology, high precision lithography technology, and electrical crosstalk suppression technology.
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